The invention relates to a video signal processing system, and in particular to a system for processing both video data and graphic data to provide a mixed output signal.
Video signal processing systems often include a filter unit that converts video pictures from a first format to a second format. For example, the first format may be coded in accordance with the digital studio standard of the International Telecommunications Union UIT-R (or of the Comite Consultatif International des Radiocommunications: CCIR) 601. An example of converting from a first format to a second format is the conversion from a PAL 16xc3x979 picture format with 720 pixels per line (P/L) and 576 lines (L), into the National Television System Committee (NTSC) 16xc3x979 picture format, with 480 pixels per line and 480 lines.
In addition, video signal processing systems often include a computing unit for mixing video and graphic pictures (e.g., layering and alpha-blending). The computing unit for mixing may weight different pictures by adjustable factors (i.e., alpha blending), so that transparent pictures can be displayed by combining and superposing the images (i.e., layering). For example, transparent buttons may be inserted while the original video picture continues to be visible in the background.
At this time, such systems exist only as individual components. A disadvantage of combining such systems is the amount of memory required to filter and mix video and graphic pictures.
Therefore, there is a need for a memory efficient video signal processing system capable of converting video signals from a first format to second format, and mixing several pictures.
Briefly, according to an aspect of the present invention, a video signal processing system for processing a video data VIN and graphic data DxcexcP includes a filter unit, which receives the video data VIN. The filter unit filters the video data VIN to convert the video data VIN into video pictures formated with a different number of columns and/or lines, and provides a filtered video signal indicative thereof. The filter unit buffers individual pixels and/or lines in a first memory device. A second memory device receives and stores the graphic data DxcexcP and the filtered video signal and provides stored signals indicative thereof. A third memory device is connected to the second memory, and stores data received from the second memory device. A mixing unit receives and mixes the stored graphic data and the stored filtered video data to provide a video output signal VOUT.
In one embodiment, the video signal processing system may be implemented with a programmable logic module (e.g., a FPCA) and additional memory units. For example, the first and third memories may be implemented as RAM external to the programmable logic module, while the second memory is located on the programmable logic module and configured as a cache to provide fast access. The remaining components of the video signal processing system may be located on the programmable logic module.
The graphic data may include bitmaps that are provided by a microprocessor. In this way, for example, transparent buttons may be inserted, while the original video picture associated with the video data continues to be visible in the background.
The system may also include a controller that controls the processing of the video and graphic signals, and specifically the programmable logic module and the memory components. The controller may be located within the programmable logic module. The controller may include a microprocessor, or receive instructions from an external microprocessor. The microprocessor may control parts of the program execution or the entire execution of the digital video signal processing program.
The video signal processing system preferably operates in real time.
In an alternative embodiment, the video signal processing system for processing a video data VIN and graphic data DxcexcP, comprising a horizontal filter that receives the a video data VIN and converts the video data VIN into video pictures formatted with a different number of columns, and provides a horizontally filtered video signal indicative thereof, wherein the horizontal filter buffers individual pixels and/or lines in a first memory device. A second memory device receives and stores the graphic data DxcexcP and the filtered video signal, and provides stored signals indicative thereof. A third memory device is connected to the second memory, and stores data received from the second memory device. A mixing and filtering unit receives the stored graphic data and the stored horizontally filtered video data, and vertically filters the stored horizontally filtered video data to convert the video data into video pictures with a different number of lines. The mixing and filtering unit provides a vertically filtered signal indicative thereof and mixes the stored graphic data with the vertically filtered video signal to provide a video output signal VOUT.
Significanlty, in this alternative embodiment, the vertical filter is no longer implemented at the input in the filter block, but at the output of the so-called layering block. This makes an additional filter block memory at the signal/video signal input unnecessary since the additional existing memory can be used at the same time.
In a preferred embodiment, the first memory is configured as a fast cache memory and the second memory as working memory in the form of a random access memory.
The system of the present invention may be used for an interlace progressive conversion. This is needed for future displays with higher resolution. In principle, the same saving applies there, mainly of a CPU, which is situated directly before the vertical filter of the first arrangement, and of an external memory. The memory saving in this case is even much greater, since the previous technique requires an additional half-picture memory for the corresponding signal processing. For example, in the case of the PAL standard, two lines must be interim stored in an external RAM. The second embodiment described herein may perform the interlace progressive version with the existing CPU and memory.